Impact of Process Variation on Parametric Performance of FinFET Transistors – Stress-aware Variability Control

Transistor Variability due to Process Variation requires in-depth characterization during technology development. Variability ranges are usually studied by layout experiments or process experiments. Some of the sensitivities responsible for variability have a purely geometric component, and others have a more complex nature. This study investigates 7nm FinFET device variability due to process variations which modulate mechanical stress in (or close to) the transistor and impacts channel carrier mobility, eventually contributing to an overall performance variability. In addition to the layout variants, which modulate stress, and which can be measured in transistors in test structures, we used a calibrated device simulator to study the changes due to process-related factors, such as variation of gate height, diffusion break width, or gate spacer thickness. We quantified each effect and compared their contribution to device performance variability.