Impact of the Inter-Fin Space on Stress Modulation and FinFET Transistor Performance

As microelectronic devices continue to scale down, the complexities of their integration and design become increasingly intricate. This study investigates the impact of fin pitch variability on stress modulation and performance in 7nm FinFET transistors. Variations in critical dimension (CD) during patterning can modulate fin width and spacing, causing undesired effects and change of device characteristics. In this work we measured device sensitivity using a comprehensive set of test structures (designed to electrically quantify the effect of fin pitch variability) as well as performed TCAD simulation of the measured devices. The results confirm device sensitivity to inter-fin space and the simulation highlights the dominant role of stress modulation due to variation of Source/Drain stressor volume. NMOS devices show gradual degradation of performance with larger inter-fin space and PMOS devices show a weaker response due to counterbalancing stress components. The study underscores the importance of fin pitch control in reduction of transistor performance variability, providing valuable insights for optimization of FinFET technologies.