A reconfigurable, high-impedance, DC-coupled low-frequency digital acquisition front-end (DAFE) suitable to operate under a power supply voltage ranging from 0.2 to IV down to 600 pW power is presented in this paper. Matching-indifferent DC accuracy over a rail-to-rail input range is uniquely achieved by the new time-multiplexed digital differential amplification technique at ultra-low area and without chopping and auto-zeroing. A 180 nm testchip of the proposed DAFE occupies 0.00945 mm2 and draws 4.5 nW at a 0.4 V supply, has a 120 Hz gain-bandwidth product, with an in-band input noise of 11.3 μVrms, a 137 μV input offset voltage standard deviation, 65.7dB CMRR, 63.8dB PSRR, and provides a 46.5dB-SFDR, 6.9 bit-ENOB digitized output at -12 dBFS.

A 0.01mm2, 0.4V-VDD, 4.5nW-Power DC-Coupled Digital Acquisition Front-End Based on Time-Multiplexed Digital Differential Amplification

Richelli A.
2022-01-01

Abstract

A reconfigurable, high-impedance, DC-coupled low-frequency digital acquisition front-end (DAFE) suitable to operate under a power supply voltage ranging from 0.2 to IV down to 600 pW power is presented in this paper. Matching-indifferent DC accuracy over a rail-to-rail input range is uniquely achieved by the new time-multiplexed digital differential amplification technique at ultra-low area and without chopping and auto-zeroing. A 180 nm testchip of the proposed DAFE occupies 0.00945 mm2 and draws 4.5 nW at a 0.4 V supply, has a 120 Hz gain-bandwidth product, with an in-band input noise of 11.3 μVrms, a 137 μV input offset voltage standard deviation, 65.7dB CMRR, 63.8dB PSRR, and provides a 46.5dB-SFDR, 6.9 bit-ENOB digitized output at -12 dBFS.
2022
978-1-6654-8494-7
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11379/571754
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